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All flip-flop outputs have 3-state buffers to separate these outputs (I/O0 to I/O7) such, that they can serve as data inputs in the parallel load mode. The serial outputs (Q0 and Q7) are used for expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset input(MR) overrides the Sn and clock (CP) inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is either state, provided that the recommended set-up and hold times, relative to the rising edge of CP, are observed.
A HIGH signal on the 3-state output enable inputs (OE1 or OE2) disables the 3-state buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1, when in preparation for a parallel load operation.
Features:
Multiplexed inputs/outputs provide improved bit density
Four operating modes: shift left, shift right, hold (store), and load data
Operates with output enable or at high-impedance OFF-state (Z)
3-state outputs drive bus lines directly
Can be cascaded for n-bits word length
Output capability: bus driver (parallel I/Os),standard (serial outputs)
ICC category: MSI
SOIC 20 package. Actual brand may vary from picture.
G357S
G357S - 74HC299 SMD 8-Bit 3-State Universal Shift Register
Detailed Description
The 74HC299 are high-speed Si-gate CMOS devicesand are pin compatible with low power Schottky TTL(LSTTL). The 74HC299 contain eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the mode select inputs (S0 and S1), as shown in the mode select table.All flip-flop outputs have 3-state buffers to separate these outputs (I/O0 to I/O7) such, that they can serve as data inputs in the parallel load mode. The serial outputs (Q0 and Q7) are used for expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset input(MR) overrides the Sn and clock (CP) inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is either state, provided that the recommended set-up and hold times, relative to the rising edge of CP, are observed.
A HIGH signal on the 3-state output enable inputs (OE1 or OE2) disables the 3-state buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1, when in preparation for a parallel load operation.
Features:
Multiplexed inputs/outputs provide improved bit density
Four operating modes: shift left, shift right, hold (store), and load data
Operates with output enable or at high-impedance OFF-state (Z)
3-state outputs drive bus lines directly
Can be cascaded for n-bits word length
Output capability: bus driver (parallel I/Os),standard (serial outputs)
ICC category: MSI
SOIC 20 package. Actual brand may vary from picture.
G357S
WARNING: This product can expose you to chemicals including lead, which is known to the State of California to cause cancer. For more information, go to www.P65Warnings.ca.gov - Why is this here?
