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Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be terminated by the overriding clear. Input pulse width may be of any duration relative to the output pulse width. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. With Rext = 2.0 kW and Cext = 0, a typical output pulse of 30 nanoseconds is achieved. Output rise and fall times are independent of pulse length.
Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 mF), and greater than one decade of timing resistance (2.0 to 100 kW for the SN74LS221N). Pulse width is defined by the relationship: tw(out) = CextRext ln 2.0 9 0.7 Cext Rext; where tW is in ns if Cext is in pF and Rext is in kW. If pulse cutoff is not critical, capacitance up to 1000 mF and resistance as low as 1.4 kW may be used. The range of jitter-free pulse widths is extended if VCC is 5.0 V and 25?C temperature.
Features:
Dual Highly Stable One-Shot
Overriding Clear Terminates Output Pulse
Pin Out is Identical to SN74LS123
16 pin DIP. Manufactured by Motorola.
A11054
A11054 - SN74LS221N Dual Monostable Multivibrators (Motorola)
Detailed Description
Each multivibrator of the SN74LS221N features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger input circuitry for B input allows jitter-free triggering for inputs as slow as 1 volt/ second, providing the circuit with excellent noise immunity. A high immunity to VCC noise is also provided by internal latching circuitry.Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be terminated by the overriding clear. Input pulse width may be of any duration relative to the output pulse width. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. With Rext = 2.0 kW and Cext = 0, a typical output pulse of 30 nanoseconds is achieved. Output rise and fall times are independent of pulse length.
Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 mF), and greater than one decade of timing resistance (2.0 to 100 kW for the SN74LS221N). Pulse width is defined by the relationship: tw(out) = CextRext ln 2.0 9 0.7 Cext Rext; where tW is in ns if Cext is in pF and Rext is in kW. If pulse cutoff is not critical, capacitance up to 1000 mF and resistance as low as 1.4 kW may be used. The range of jitter-free pulse widths is extended if VCC is 5.0 V and 25?C temperature.
Features:
Dual Highly Stable One-Shot
Overriding Clear Terminates Output Pulse
Pin Out is Identical to SN74LS123
16 pin DIP. Manufactured by Motorola.
A11054
WARNING: This product can expose you to chemicals including lead, which is known to the State of California to cause cancer. For more information, go to www.P65Warnings.ca.gov - Why is this here?
