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The outputs are transparent to the inputs when latch enable (LE) is high. When LE is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. The latch operation is independent of output-enable (OE\) input. OE\ can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. When OE\ is high, the outputs are in the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The 74FCT373 is characterized for operation from 0°C to 70°C.
Features:
BiCMOS Technology With Low Quiescent Power
Buffered Inputs
Noninverted Outputs
Input/Output Isolation From VCC
48-mA Output Sink Current
Controlled Output Edge Rates
Output Voltage Swing Limited to 3.7 V
SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
SOIC 20 package. Actual brand may vary from picture.
G390S
G390S - 74FCT373 SMD BiCMOS FCT Octal Transparent Latch
Detailed Description
The 74FCT373 is an octal, transparent, D-type latch with 3-state outputs using a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.The outputs are transparent to the inputs when latch enable (LE) is high. When LE is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. The latch operation is independent of output-enable (OE\) input. OE\ can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. When OE\ is high, the outputs are in the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The 74FCT373 is characterized for operation from 0°C to 70°C.
Features:
BiCMOS Technology With Low Quiescent Power
Buffered Inputs
Noninverted Outputs
Input/Output Isolation From VCC
48-mA Output Sink Current
Controlled Output Edge Rates
Output Voltage Swing Limited to 3.7 V
SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
SOIC 20 package. Actual brand may vary from picture.
G390S
WARNING: This product can expose you to chemicals including lead, which is known to the State of California to cause cancer. For more information, go to www.P65Warnings.ca.gov - Why is this here?
